High Speed Digital Electrical Design and Encryption Security Expert

Technical Consultant #1920

High speed digital design: XAUI, PCIe, Interlaken, 10GBase-KR
Network processor design: Marvell AX240, EzChip NPA
Memory design: DDR2/DDR3 SDRAM, QDR SRAM, NAND, NOR
Processor design: PowerPC, Cavium MIPs, Intel Xscale (ARMv7)
Encryption: DES, 3DES, AES, RSA, MD5, SHA-1, others
Communications: Ethernet: 10GBase-X, 10/100/1000Base-T, SONET, ATM, RS-232, PPP, MLPPP, X86, DS-3, DS-1
Signal integrity analysis: Hyperlynx, HSPICE, Cadence Allegro PCI SI
CAD tools: Mentor Graphics DxDesigner, Cadence Allegro, OrCAD, PADS
Operating systems: Linux, VxWorks
FPGA/CPLD design: Altera, Xilinx, Lattice designs in VHDL and Verilog
Software: C/C++ for Linux device drivers and Hardware Abstraction Layer, (HAL)
Testing: EMI, ESD, Homologation, HALT/HASS, JTAG, BIST
Timing: IEEE 1588v2, Sync-E, SONET

Undisclosed Company, Senior Staff Engineer, 2008 - 2012

Chief Architect and Principal hardware designer for Carrier Ethernet class aggregation and customer premises products.

Multi-10Gbps Carrier Ethernet class aggregation product family.

Chief Architect and hardware designer: Responsible for the hardware and system design for a 7-card chassis based product that supported 8 10GBase-X and 72 1000Base-X Ethernet interfaces.
Designed the NPU based distributed dataplane processing complex (using multiple Marvell AX240) that performed high touch Layer-2 and Layer-3 packet processing with a combined bandwidth of 334MPPS.
Designed the 20Gbps dataplane interconnect used for card-to-card communication.
Completed design of the system wide distributed control plane processing based on the multicore Cavium family of MIPs processors.

1 Gigabit Carrier Ethernet CPE Product Family for Ethernet transport over TDM (Time-Division Multiplexing networks)

Chief Architect and hardware designer: Responsible for the control plane and dataplane main board design.
Product used a Cavium MIPs processor and an Altera FPGA for dataplane and control plane processing.
This product had a highly aggressive schedule: start-to-customer GA in only 9 months for a brand new design.

SafeNet, Morrisville, NC, Principal Scientist, 1996 - 2008

Founding partner in a start-up corporation.
Principal hardware and system architect for a set of encryption products for ATM, SONET, Ethernet and IPSEC networks.

10 Gigabit Ethernet MACsec Product Line

Chief Architect, hardware designer, and FPGA designer for a MACsec, standard based, high performance ethernet security solution.
Designed a high performance 10Gbps ethernet solution based on XFP transceivers, Marvel 10G PHY devices, Cortina 10G MAC devices and Stratix-II FPGAs.
Responsible for the hardware design of the Ethernet encrytion devices including the security and host processor complex. This design uses SafeNet developed intellectual property for MACsec encryption and KEYsec key exchange. Responsible for ensuring that the Intellectual Property developed, at four geographically remote locations, integrated smoothly in addition to designing the hardware and architecting the system.

OC-192 Type-1 SONET Encryption Product Line

Team member and system architect of a 10Gbps Classified SONET encryption product line.
Responsible for the hardware design of the 10Gbps SONET interface card and a 2.5Gbps SONET interface card.
Design included advanced PLLs for clock management, Agere ASICs, and Altera Stratix-II FPGAs.
Completed design of the Verilog HDL design for four large FPGAs.

Gigabit IPSEC Gateway Product

Chief hardware architect and designer for a multi-Gigabit IPSEC encryption product based on a dual IXP2400 Network Processor and VxWorks operating system.
Designed an embedded Network Processor based dataplane processing system with interfaces to QDR SSRAM, DDR SDRAM and Xilinx Virtex-II FPGAs.

Cost reduction team leader

Chief architect and hardware designer for a cost reduction effort that reduced the CoGs of our encryption products by more than 75%.

ASIC design

Team member of a three-man design team that produced a 250,000 gate ASIC for an OC-3c rate ATM encryption product.

ATM encryption product

Architect for an FPGA based ATM encryptor that operated at rates from 1.5Mbps up to 622Mbps full duplex.
Responsible for start-up, hardware design, FPGA design, PCB board design, and software design.

MCNC, RTP, NC, Research Engineer, 1990 - 1996

Principle Investigator and hardware designer for state-of-the-art research projects in communication and network security.

ATM traffic analysis and encryption research

Principle investigator of a series of DARPA funded projects to design, build, and test the traffic characteristics and security of OC-12c rate ATM networks: Designed the hardware for the first demonstrable non-classified encryption technology for ATM networks operating at OC-12c rates.

ATM networking research

Hardware designer for a DARPA/NFS funded project to prove the feasibility of distributed supercomputing over high speed wide-area networks.
Responsible for the hardware design for an 800Mbps traffic analysis system.

Nortel, RTP, NC, Research Engineer, 1985 - 1990

PCB design research

Team Leader of a research group that investigated transmission-line effects of printed circuit board design on high-speed digital signals.

Central Office switching equipment design

Designed Telco-class central office switching equipment; along with a team responsible for the design of the power subsystems and cable assemblies.

Patents